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EURODAC
1990
IEEE
72views VHDL» more  EURODAC 1990»
13 years 8 months ago
CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler
J. Zegers, Paul Six, Jan M. Rabaey, Hugo De Man
DAC
2003
ACM
14 years 5 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...