63 search results - page 1 / 13 » CMOS gate modeling based on equivalent inverter |
ISCAS
1999
IEEE
13 years 8 months ago
1999
IEEE
A method for modeling complex CMOS gates by the reduction of each gate to an effective equivalent inverter is introduced. The conducting and parasitic behavior of parallel and ser...
TCAD
2010
13 years 2 months ago
2010
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as a new unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the...
DAC
1996
ACM
13 years 8 months ago
1996
ACM
: While delay modeling of gates with a single switching input has received considerable attention, the case of multiple inputs switching in close temporal proximity is just beginni...
GLVLSI
2003
IEEE
13 years 9 months ago
2003
IEEE
- A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain ...