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» CMOS gate modeling based on equivalent inverter
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ISCAS
1999
IEEE
99views Hardware» more  ISCAS 1999»
9 years 4 months ago
CMOS gate modeling based on equivalent inverter
A method for modeling complex CMOS gates by the reduction of each gate to an effective equivalent inverter is introduced. The conducting and parasitic behavior of parallel and ser...
Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioa...
TCAD
2010
106views more  TCAD 2010»
8 years 10 months ago
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimo...
ISCAS
2005
IEEE
224views Hardware» more  ISCAS 2005»
9 years 5 months ago
A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter
— A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as a new unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the...
Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga
DAC
1996
ACM
9 years 4 months ago
Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time
: While delay modeling of gates with a single switching input has received considerable attention, the case of multiple inputs switching in close temporal proximity is just beginni...
V. Chandramouli, Karem A. Sakallah
GLVLSI
2003
IEEE
229views VLSI» more  GLVLSI 2003»
9 years 5 months ago
Design issues in low-voltage high-speed current-mode logic buffers
- A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain ...
Payam Heydari
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