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CMP on SoC: Architect's View
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ISSS
2002
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CMP on SoC: Architect's View
13 years 9 months ago
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Shuichi Sakai
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2005
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Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
14 years 1 months ago
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As technology scales, power consumption and thermal effects have become challenges for system-on-chip designers. The rising on-chip temperatures can have negative impacts on SoC p...
Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vi...
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