869 search results - page 1 / 174 » Cache Architectures for Reconfigurable Hardware |
ERSA
2006
13 years 5 months ago
2006
The architecture and use of caches for two-level reconfigurable hardware is studied in this paper. The considered two-level reconfigurable hardware performs ordinary reconfiguratio...
MICRO
2000
IEEE
13 years 8 months ago
2000
IEEE
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
CASES
2007
ACM
13 years 8 months ago
2007
ACM
We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to p...
DAC
2000
ACM
13 years 8 months ago
2000
ACM
– This paper describes the system design and implementation of Active Basestations, a novel application of the run-time reconfigurable hardware technology whose applications have...
FPL
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. This work discusses the Memory Architecture for Reconfigurable Computers (MARC), a scalable, device-independent memory interface that supports both irregular (via configu...