31 search results - page 1 / 7 » Cache-aware scheduling and analysis for multicores |
ECRTS
2009
IEEE
13 years 2 months ago
2009
IEEE
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
ECRTS
2008
IEEE
13 years 11 months ago
2008
IEEE
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
IEEECIT
2010
IEEE
13 years 3 months ago
2010
IEEE
Current hard real-time scheduling and analysis techniques are unable to efficiently utilize the computational bandwidth provided by multicore platforms. This is due to the large ...
IWMM
2011
Springer
12 years 7 months ago
2011
Springer
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
JSA
2011
12 years 7 months ago
2011
The importance of accounting for interrupts in multiprocessor real-time schedulability analsysis is discussed and three interrupt accounting methods, namely quantum-centric, task-...