55 search results - page 4 / 11 » Caches and Hash Trees for Efficient Memory Integrity |
DAC
2008
ACM
14 years 7 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
ASIACRYPT
2007
Springer
13 years 10 months ago
2007
Springer
In an effort to design a MAC scheme that is built using block cipher components and runs faster than the modes of operation for message authentication, Daemen and Rijmen have propo...
ANSS
2004
IEEE
13 years 10 months ago
2004
IEEE
To enable optimizations in memory access behavior of high performance applications, cache monitoring is a crucial process. Simulation of cache hardware is needed in order to allow...
ERLANG
2003
ACM
13 years 11 months ago
2003
ACM
The viability of implementing an in-memory database, Erlang ETS, using a relatively-new data structure, called a Judy array, was studied by comparing the performance of ETS tables...
TVCG
2010
13 years 26 days ago
2010
Abstract--One important bottleneck when visualizing large data sets is the data transfer between processor and memory. Cacheaware (CA) and cache-oblivious (CO) algorithms take into...