169 search results - page 1 / 34 » Caching queues in memory buffers |
SODA
2004
ACM
13 years 6 months ago
2004
ACM
Motivated by the need for maintaining multiple, large queues of data in modern high-performance systems, we study the problem of caching queues in memory under the following simpl...
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
SPAA
2004
ACM
13 years 10 months ago
2004
ACM
We present the Buffer Heap (BH), a cache-oblivious priority queue that supports Delete-Min, Delete, and Decrease-Key operations in O( 1 B log2 N B ) amortized block transfers fro...
ISCA
1989
IEEE
13 years 9 months ago
1989
IEEE
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...