170 search results - page 1 / 34 » Challenges in Embedded Memory Design and Test |
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to upd...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
DDECS
2008
IEEE
13 years 11 months ago
2008
IEEE
— Testing SoC is a challenging task, especially when addressing complex and highfrequency devices. Among the different techniques that can be exploited, Software-Based Selft-Test...
MTDT
2000
IEEE
13 years 9 months ago
2000
IEEE
A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a give...