Sciweavers

38 search results - page 3 / 8
» Characterizing non-deterministic circuit size
Sort
View
ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
14 years 3 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
JGT
2007
146views more  JGT 2007»
13 years 6 months ago
Compatible circuit decompositions of 4-regular graphs
A transition system T of an Eulerian graph G is a family of partitions of the edges incident to each vertex of G into transitions i.e. subsets of size two. A circuit decomposition...
Herbert Fleischner, François Genest, Bill J...
DATE
2003
IEEE
98views Hardware» more  DATE 2003»
13 years 11 months ago
On the Characterization of Hard-to-Detect Bridging Faults
We investigate a characterization of hard-to-detect bridging faults. For circuits with large numbers of lines (or nodes), this characterization can be used to select target faults...
Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
LICS
1998
IEEE
13 years 10 months ago
On Proofs about Threshold Circuits and Counting Hierarchies
Hierarchies (Extended Abstract) Jan Johannsen Chris Pollett Department of Mathematics Department of Computer Science University of California, San Diego Boston University La Jolla,...
Jan Johannsen, Chris Pollett
ISCAS
2007
IEEE
173views Hardware» more  ISCAS 2007»
14 years 17 days ago
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
Riaz Naseer, Younes Boulghassoul, Jeff Draper, San...