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ICFEM
2009
Springer
13 years 3 months ago
Graded-CTL: Satisfiability and Symbolic Model Checking
In this paper we continue the study of a strict extension of the Computation Tree Logic, called graded-CTL, recently introduced by the same authors. This new logic augments the sta...
Alessandro Ferrante, Margherita Napoli, Mimmo Pare...
ICCD
1995
IEEE
109views Hardware» more  ICCD 1995»
13 years 9 months ago
Verifying the performance of the PCI local bus using symbolic techniques
Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware desig...
Sérgio Vale Aguiar Campos, Edmund M. Clarke...
MTV
2006
IEEE
98views Hardware» more  MTV 2006»
14 years 6 days ago
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy...
RV
2010
Springer
220views Hardware» more  RV 2010»
13 years 4 months ago
Runtime Verification with the RV System
The RV system is the first system to merge the benefits of Runtime Monitoring with Predictive Analysis. The Runtime Monitoring portion of RV is based on the successful Monitoring O...
Patrick O'Neil Meredith, Grigore Rosu
IJCV
2008
146views more  IJCV 2008»
13 years 6 months ago
Scanning Depth of Route Panorama Based on Stationary Blur
This work achieves an efficient acquisition of scenes and their depths along long streets. A camera is mounted on a vehicle moving along a straight or a mildly curved path and a sa...
Jiang Yu Zheng, Min Shi