56 search results - page 2 / 12 » Chip and PIN is Broken |
GLVLSI
1999
IEEE
13 years 8 months ago
1999
IEEE
This paper presents an area pad layout method to e ciently reduce the space required for interconnection pads and pad drivers. Unlike peripheral pads, area pads use only the top m...
ASPLOS
2008
ACM
13 years 6 months ago
2008
ACM
ASPDAC
1998
ACM
13 years 8 months ago
1998
ACM
ISQED
2003
IEEE
13 years 9 months ago
2003
IEEE
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
ASPDAC
1999
ACM
13 years 8 months ago
1999
ACM
A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on...