45 search results - page 9 / 9 » Circuit simulation based obstacle-aware Steiner routing |
ISPD
2003
ACM
13 years 9 months ago
2003
ACM
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
ISPD
2007
ACM
13 years 6 months ago
2007
ACM
When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
FPGA
2003
ACM
13 years 9 months ago
2003
ACM
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...