2 search results - page 1 / 1 » Clock Grouping: A Low Cost DFT Methodology for Delay Testing |
DAC
1994
ACM
13 years 8 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
IOLTS
2005
IEEE
13 years 9 months ago
2005
IEEE
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...