15 search results - page 3 / 3 » Clock Network Synthesis with Concurrent Gate Insertion |
IJCSS
2007
13 years 5 months ago
2007
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
EMSOFT
2004
Springer
13 years 11 months ago
2004
Springer
Dataflow synchronous languages have attracted considerable interest in domains such as real-time control and hardware design. The potential benefits are promising: Discrete-time...
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
Abstract—Supporting Distributed Shared Memory (DSM) is essential for multi-core Network-on-Chips for the sake of reusing huge amount of legacy code and easy programmability. We p...
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...