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» Clock tree synthesis with data-path sensitivity matching
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FPGA
1992
ACM
176views FPGA» more  FPGA 1992»
13 years 9 months ago
Minimization of Permuted Reed-Muller Trees for Cellular Logic
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path...
Li-Fei Wu, Marek A. Perkowski