Sciweavers

11 search results - page 1 / 3
» Clocking structures and power analysis for nanomagnet-based ...
Sort
View
ISLPED
2007
ACM
142views Hardware» more  ISLPED 2007»
13 years 6 months ago
Clocking structures and power analysis for nanomagnet-based logic devices
Michael T. Niemier, M. Alam, Xiaobo Sharon Hu, Gar...
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
13 years 10 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
ISCA
2005
IEEE
166views Hardware» more  ISCA 2005»
13 years 10 months ago
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
Emil Talpes, Diana Marculescu
ICCD
2006
IEEE
312views Hardware» more  ICCD 2006»
14 years 1 months ago
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
Kimiyoshi Usami, Naoaki Ohkubo
DAMON
2006
Springer
13 years 8 months ago
Processing-in-memory technology for knowledge discovery algorithms
The goal of this work is to gain insight into whether processingin-memory (PIM) technology can be used to accelerate the performance of link discovery algorithms, which represent ...
Jafar Adibi, Tim Barrett, Spundun Bhatt, Hans Chal...