47 search results - page 8 / 10 » Co-design of interleaved memory systems |
ISCA
1996
IEEE
13 years 10 months ago
1996
IEEE
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
ICFP
2008
ACM
14 years 5 months ago
2008
ACM
Transactional events (TE) are an approach to concurrent programming that enriches the first-class synchronous message-passing of Concurrent ML (CML) with a combinator that allows ...
ACSD
2003
IEEE
13 years 11 months ago
2003
IEEE
— We consider the problem of specifying a model of the Zero Copy Secured Protocol for the purpose of LTL verification with the SPIN Model Checker. ZCSP is based on Direct Memory...
HPDC
2012
IEEE
11 years 8 months ago
2012
IEEE
Consider a multithreaded parallel application running inside a multicore virtual machine context that is itself hosted on a multi-socket multicore physical machine. How should the...
ASPLOS
2010
ACM
13 years 9 months ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...