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» Co-design of interleaved memory systems
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POPL
2009
ACM
14 years 6 months ago
Feedback-directed barrier optimization in a strongly isolated STM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
Nathan Grasso Bronson, Christos Kozyrakis, Kunle O...
MM
2004
ACM
121views Multimedia» more  MM 2004»
13 years 10 months ago
A framework for robust and scalable audio streaming
We propose a framework to achieve bandwidth efficient, error robust and bitrate scalable audio streaming. Our approach is compatible with most audio compression format. The main c...
Ye Wang, Wendong Huang, Jari Korhonen
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 6 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...
CCGRID
2009
IEEE
14 years 2 days ago
Improving Parallel Write by Node-Level Request Scheduling
In a cluster of multiple processors or cpu-cores, many processes may run on each compute node. Each process tends to issue contiguous I/O requests for snapshot, checkpointing or s...
Kazuki Ohta, Hiroya Matsuba, Yutaka Ishikawa
CC
2003
Springer
114views System Software» more  CC 2003»
13 years 10 months ago
Combined Code Motion and Register Allocation Using the Value State Dependence Graph
We define the Value State Dependence Graph (VSDG). The VSDG is a form of the Value Dependence Graph (VDG) extended by the addition of state dependence edges to model sequentialise...
Neil Johnson, Alan Mycroft