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» CoarseZ Buffer Bandwidth Model in 3D Rendering Pipeline
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IMSCCS
2006
IEEE
13 years 10 months ago
CoarseZ Buffer Bandwidth Model in 3D Rendering Pipeline
Depth traffic occupies a major portion of 3D graphics memory bandwidth. In order to reduce depth reading, we propose employing a low-resolution depth buffer, namely CoarseZ buffer...
Ke Yang, Ke Gao, Jiaoying Shi, Xiaohong Jiang, Hua...
CODES
2000
IEEE
13 years 9 months ago
Memory architecture for efficient utilization of SDRAM: a case study of the computation/memory access trade-off
This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance require...
Thomas Gleerup, Hans Holten-Lund, Jan Madsen, Stee...
SI3D
2005
ACM
13 years 10 months ago
What you see is what you snap: snapping to geometry deformed on the GPU
We present a simple yet effective snapping technique for constraining the motion of the cursor of an input device to the surface of 3D models whose geometry is arbitrarily deforme...
Harlen Costa Batagelo, Shin-Ting Wu
SIGGRAPH
2000
ACM
13 years 8 months ago
The WarpEngine: an architecture for the post-polygonal age
We present the WarpEngine, an architecture designed for realtime image-based rendering of natural scenes from arbitrary viewpoints. The modeling primitives are real-world images w...
Voicu Popescu, John G. Eyles, Anselmo Lastra, Josh...
SIGGRAPH
1999
ACM
13 years 8 months ago
Realistic, Hardware-Accelerated Shading and Lighting
With fast 3D graphics becoming more and more available even on low end platforms, the focus in hardware-accelerated rendering is beginning to shift towards higher quality renderin...
Wolfgang Heidrich, Hans-Peter Seidel