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ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 7 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy