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ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
13 years 10 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
ICCS
2007
Springer
13 years 9 months ago
Hamiltonian Connected Line Graphs
1 A graph G is hamiltonian-connected if any two of its vertices are connected by a Hamilton2 path (a path including every vertex of G); and G is s-hamiltonian-connected if the del...
Dengxin Li, Hong-Jian Lai, Yehong Shao, Mingquan Z...
SYNASC
2005
IEEE
129views Algorithms» more  SYNASC 2005»
13 years 10 months ago
Logic Restructuring for Delay Balancing in Wave-Pipelined Circuits: An Integer Programming Approach
In this paper we apply integer programming (IP) based techniques to the problem of delay balancing in wave-pipelined circuits. The proposed approach considers delays, as well as f...
Srivastav Sethupathy, Nohpill Park, Marcin Paprzyc...
PPSC
1997
13 years 6 months ago
A Coarse-Grain Parallel Formulation of Multilevel k-way Graph Partitioning Algorithm
In this paper we present a parallel formulation of a multilevel k-way graph partitioning algorithm, that is particularly suited for message-passing libraries that have high latenc...
George Karypis, Vipin Kumar
VRML
1998
ACM
13 years 9 months ago
Simplicial Maps for Progressive Transmission of Polygonal Surfaces
We present a new method for (1) automatically generating multiple Levels Of Detail (LODs) of a polygonal surface, (2) progressively loading, or transmitting, and displaying a surf...
André Guéziec, Gabriel Taubin, Franc...