Sciweavers

Share
32 search results - page 1 / 7
» Combining Decision Diagrams and SAT Procedures for Efficient...
Sort
View
CAV
2000
Springer
187views Hardware» more  CAV 2000»
11 years 8 months ago
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
In this paper we show how to do symbolic model checking using Boolean Expression Diagrams (BEDs), a non-canonical representation for Boolean formulas, instead of Binary Decision Di...
Poul Frederick Williams, Armin Biere, Edmund M. Cl...
FMCAD
1998
Springer
11 years 9 months ago
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
Sergey Berezin, Armin Biere, Edmund M. Clarke, Yun...
SAT
2005
Springer
123views Hardware» more  SAT 2005»
11 years 10 months ago
Bounded Model Checking with QBF
Current algorithms for bounded model checking (BMC) use SAT methods for checking satisfiability of Boolean formulas. These BMC methods suffer from a potential memory explosion prob...
Nachum Dershowitz, Ziyad Hanna, Jacob Katz
MEMOCODE
2006
IEEE
11 years 11 months ago
Mixed symbolic representations for model checking software programs
We present an efficient symbolic search algorithm for software model checking. The algorithm combines multiple symbolic representations to efficiently represent the transition r...
Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivanc...
ISQED
2002
IEEE
175views Hardware» more  ISQED 2002»
11 years 10 months ago
On the Relation between SAT and BDDs for Equivalence Checking
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Diagrams (BDDs) and SAT...
Sherief Reda, Rolf Drechsler, Alex Orailoglu
books