32 search results - page 7 / 7 » Combining Decision Diagrams and SAT Procedures for Efficient... |
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
CADE
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. The problem of computing Craig interpolants in SMT has recently received a lot of interest, mainly for its applications in formal verification. Efficient algorithms for ...