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» Combining Software and Hardware Verification Techniques
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FMSD
2002
128views more  FMSD 2002»
13 years 4 months ago
Combining Software and Hardware Verification Techniques
Combining verification methods developed separately for software and hardware is motivated by the industry's need for a technology that would make formal verification of reali...
Robert P. Kurshan, Vladimir Levin, Marius Minea, D...
EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
13 years 8 months ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel
DAC
2006
ACM
14 years 5 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu
RV
2010
Springer
171views Hardware» more  RV 2010»
13 years 2 months ago
Runtime Verification for Software Transactional Memories
Software transactional memories (STMs) promise simple and efficient concurrent programming. Several correctness properties have been proposed for STMs. Based on a bounded conflict ...
Vasu Singh
TAP
2008
Springer
144views Hardware» more  TAP 2008»
13 years 4 months ago
Integrating Verification and Testing of Object-Oriented Software
Formal methods can only gain widespread use in industrial software development if they are integrated into software development techniques, tools, and languages used in practice. A...
Christian Engel, Christoph Gladisch, Vladimir Kleb...