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ICPP
2008
IEEE
14 years 13 days ago
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
Lei Jin, Sangyeun Cho
HPCA
2008
IEEE
14 years 6 months ago
Runahead Threads to improve SMT performance
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
Tanausú Ramírez, Alex Pajuelo, Olive...
EUROPAR
2003
Springer
13 years 11 months ago
Compiler-Assisted Thread Level Control Speculation
Abstract. This paper proposes two compiler-assisted techniques to improve thread level control speculation in speculative multithreading executions. The first technique is to incr...
Hideyuki Miura, Luong Dinh Hung, Chitaka Iwama, Da...
IEEEPACT
2000
IEEE
13 years 10 months ago
Address Partitioning in DSM Clusters with Parallel Coherence Controllers
Recent research suggests that DSM clusters can benefit from parallel coherence controllers. Parallel controllers require address partitioning and synchronization to avoid handlin...
Ilanthiraiyan Pragaspathy, Babak Falsafi
IPPS
1999
IEEE
13 years 10 months ago
The MuSE System: A Flexible Combination of On-Stack Execution and Work-Stealing
Executing subordinate activities by pushing return addresses on the stack is the most e cient working mode for sequential programs. It is supported by all current processors, yet i...
Markus Leberecht