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» Communication latency aware low power NoC synthesis
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DAC
2006
ACM
14 years 4 months ago
Communication latency aware low power NoC synthesis
Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham...
CODES
2006
IEEE
13 years 9 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha
HOTI
2008
IEEE
13 years 10 months ago
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication
As processor core counts increase, networks-on-chip (NoCs) are becoming an increasingly popular interconnection fabric due to their ability to supply high bandwidth. However, NoCs...
Tushar Krishna, Amit Kumar 0002, Patrick Chiang, M...
AHS
2006
IEEE
152views Hardware» more  AHS 2006»
13 years 9 months ago
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
Balal Ahmad, Ahmet T. Erdogan, Sami Khawam
NOCS
2007
IEEE
13 years 10 months ago
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing
Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implemen...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...