19 search results - page 3 / 4 » Communication latency aware low power NoC synthesis |
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the trans...
TC
2008
13 years 5 months ago
2008
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
CGO
2004
IEEE
13 years 8 months ago
2004
IEEE
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
NOCS
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
MSWIM
2005
ACM
13 years 10 months ago
2005
ACM
We investigate the impact of power control on latency in wireless ad-hoc networks. If transmission power is increased, interference increases, thus reducing network capacity. A no...