14 search results - page 1 / 3 » Compact modelling of Through-Silicon Vias (TSVs) in three-di... |
3DIC
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
NANONET
2009
Springer
13 years 9 months ago
2009
Springer
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
SLIP
2009
ACM
13 years 11 months ago
2009
ACM
Individual dies in 3D integrated circuits are connected using throughsilicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power ...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract—This work proposes reliability aware through silicon via (TSV) planning for the 3D stacked silicon integrated circuits (ICs). The 3D power distribution network is modele...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger a...