59 search results - page 2 / 12 » Comparing the latency performance of the DTable and DRR sche... |
AINA
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we study the problem of scheduling messages between two parallel machines connected by a low latency network during a data redistribution. We compare two approaches....
CP
2001
Springer
13 years 9 months ago
2001
Springer
Instruction scheduling is one of the most important steps for improving the performance of object code produced by a compiler. The local instruction scheduling problem is to nd a m...
JILP
2000
13 years 5 months ago
2000
Load latency remains a signi cant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Predi...
MICRO
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
Ensuring back-to-back execution of dependent instructions in a conventional out-of-order processor requires scheduling logic that wakes up and selects instructions at the same rat...