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» Compilation for Future Nanocomputer Architectures
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ICS
2005
Tsinghua U.
13 years 9 months ago
Disk layout optimization for reducing energy consumption
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
ASPLOS
1996
ACM
13 years 7 months ago
A Quantitative Analysis of Loop Nest Locality
This paper analyzes and quantifies the locality characteristics of numerical loop nests in order to suggest future directions for architecture and software cache optimizations. Si...
Kathryn S. McKinley, Olivier Temam
DNA
2008
Springer
13 years 5 months ago
A Simple DNA Gate Motif for Synthesizing Large-Scale Circuits
The prospects of programming molecular systems to perform complex autonomous tasks has motivated research into the design of synthetic biochemical circuits. Of particular interest ...
Lulu Qian, Erik Winfree