58 search results - page 3 / 12 » Compilation for Future Nanocomputer Architectures |
SAC
2009
ACM
13 years 11 months ago
2009
ACM
Parallel architectures are the way of the future, but are notoriously difficult to program. In addition to the low-level constructs they often present (e.g., locks, DMA, and non-...
CLUSTER
2008
IEEE
13 years 11 months ago
2008
IEEE
—The industry is now in agreement that the future of architecture design lies in multiple cores. As a consequence, all computer systems today, from embedded devices to petascale ...
CDES
2008
13 years 6 months ago
2008
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
APCSAC
2004
IEEE
13 years 8 months ago
2004
IEEE
As device sizes continue shrinking, lower charges are needed to activate gates, and consequently ever smaller external events (such as single ionizing particles of naturally occurr...
PPOPP
2005
ACM
13 years 10 months ago
2005
ACM
Disk subsystem is known to be a major contributor to overall power consumption of high-end parallel systems. Past research proposed several architectural level techniques to reduc...