3 search results - page 1 / 1 » Compile-time decided instruction cache locking using worst-c... |
CODES
2007
IEEE
13 years 10 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
RTAS
2008
IEEE
13 years 10 months ago
2008
IEEE
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
ECRTS
2005
IEEE
13 years 10 months ago
2005
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...