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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 5 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
CODES
2007
IEEE
13 years 8 months ago
Energy efficient co-scheduling in dynamically reconfigurable systems
Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...
Pao-Ann Hsiung, Pin-Hsien Lu, Chih-Wen Liu
ICFP
2008
ACM
14 years 4 months ago
A scheduling framework for general-purpose parallel languages
The trend in microprocessor design toward multicore and manycore processors means that future performance gains in software will largely come from harnessing parallelism. To reali...
Matthew Fluet, Mike Rainey, John H. Reppy
IPPS
2010
IEEE
13 years 2 months ago
Parallel Task for parallelizing object-oriented desktop applications
As multi-cores arrive for mainstream desktop systems, developers must invest the effort to parallelize their applications. We present Parallel Task (short ParaTask), a solution to ...
Nasser Giacaman, Oliver Sinnen
SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
12 years 12 months ago
Should we worry about memory loss?
In recent years the High Performance Computing (HPC) industry has benefited from the development of higher density multi-core processors. With recent chips capable of executing u...
O. Perks, Simon D. Hammond, S. J. Pennycook, Steph...