57 search results - page 11 / 12 » Compiler optimization and ordering effects on VLIW code comp... |
HPCA
2003
IEEE
14 years 5 months ago
2003
IEEE
Inherent within complex instruction set architectures such as x86 are inefficiencies that do not exist in a simpler ISAs. Modern x86 implementations decode instructions into one o...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
IEEEPACT
2002
IEEE
13 years 10 months ago
2002
IEEE
Java exception checks are designed to ensure that any faulting instruction causing a hardware exception does not terminate the program abnormally. These checks, however, impose so...
SIGMOD
2008
ACM
14 years 5 months ago
2008
ACM
In this paper, we present Spade - the System S declarative stream processing engine. System S is a large-scale, distributed data stream processing middleware under development at ...
MICRO
2005
IEEE
13 years 11 months ago
2005
IEEE
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...