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PPOPP
2009
ACM
11 years 1 days ago
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors
Recent advances in polyhedral compilation technology have made it feasible to automatically transform affine sequential loop nests for tiled parallel execution on multi-core proce...
Muthu Manikandan Baskaran, Nagavijayalakshmi Vydya...
IPPS
2010
IEEE
9 years 9 months ago
DynTile: Parametric tiled loop generation for parallel execution on multicore processors
Abstract--Loop tiling is an important compiler transformation used for enhancing data locality and exploiting coarsegrained parallelism. Tiled codes in which tile sizes are runtime...
Albert Hartono, Muthu Manikandan Baskaran, J. Rama...
TPDS
2010
144views more  TPDS 2010»
9 years 10 months ago
Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
David A. Zier, Ben Lee
ICPP
2008
IEEE
10 years 6 months ago
Thread-Sensitive Modulo Scheduling for Multicore Processors
This paper describes a generalisation of modulo scheduling to parallelise loops for SpMT processors that exploits simultaneously both instruction-level parallelism and thread-leve...
Lin Gao 0002, Quan Hoang Nguyen, Lian Li 0002, Jin...
CCGRID
2008
IEEE
10 years 6 months ago
Scheduling Asymmetric Parallelism on a PlayStation3 Cluster
Understanding the potential and implications of asymmetric multi-core processors for cluster computing is necessary, as these processors are rapidly becoming mainstream components...
Filip Blagojevic, Matthew Curtis-Maury, Jae-Seung ...
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