6 search results - page 1 / 2 » Compiler-generated communication for pipelined FPGA applicat... |
DAC
2003
ACM
14 years 5 months ago
2003
ACM
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
FCCM
2002
IEEE
13 years 9 months ago
2002
IEEE
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...
FPGA
2009
ACM
13 years 8 months ago
2009
ACM
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
ISCAS
2005
IEEE
13 years 9 months ago
2005
IEEE
—A high-throughput hardware architecture and FPGA implementation of the 64-bit NESSIE proposal, MISTY1 block cipher, is presented in this paper. This architecture, in contrast to...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...