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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 6 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
BMCBI
2010
125views more  BMCBI 2010»
13 years 6 months ago
A computational screen for site selective A-to-I editing detects novel sites in neuron specific Hu proteins
Background: Several bioinformatic approaches have previously been used to find novel sites of ADAR mediated A-to-I RNA editing in human. These studies have discovered thousands of...
Mats Ensterö, Örjan Åkerborg, Dani...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 5 months ago
Generating physical addresses directly for saving instruction TLB energy
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. K...
PC
2007
343views Management» more  PC 2007»
13 years 5 months ago
Runtime scheduling of dynamic parallelism on accelerator-based multi-core systems
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
Filip Blagojevic, Dimitrios S. Nikolopoulos, Alexa...
PVLDB
2008
128views more  PVLDB 2008»
13 years 5 months ago
Implementing filesystems by tree-aware DBMSs
With the rise of XML, the database community has been challenged by semi-structured data processing. Since the data type behind XML is the tree, state-of-the-art RDBMSs have learn...
Alexander Holupirek, Marc H. Scholl