82 search results - page 16 / 17 » Compiling code accelerators for FPGAs |
JRTIP
2008
13 years 4 months ago
2008
Abstract In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on Fi...
ASPLOS
2010
ACM
13 years 11 months ago
2010
ACM
This paper introduces a new abstraction to accelerate the readbarriers and write-barriers used by language runtime systems. We exploit the fact that, dynamically, many barrier exe...
FCCM
2008
IEEE
13 years 11 months ago
2008
IEEE
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
FPGA
2010
ACM
13 years 5 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...