511 search results - page 1 / 103 » Compiling for instruction cache performance on a multithread... |
MICRO
2002
IEEE
13 years 9 months ago
2002
IEEE
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
MICRO
1998
IEEE
13 years 8 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
MICRO
1997
IEEE
13 years 8 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
IPPS
2003
IEEE
13 years 9 months ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
IPPS
2010
IEEE
13 years 2 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...