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» Complexity Of Minimum-Delay Gate Resizing
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VLSID
2001
IEEE
98views VLSI» more  VLSID 2001»
11 years 1 months ago
Complexity Of Minimum-Delay Gate Resizing
Supratik Chakraborty, Rajeev Murgai
ICCAD
1999
IEEE
88views Hardware» more  ICCAD 1999»
10 years 5 months ago
Performance optimization under rise and fall parameters
Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performan...
Rajeev Murgai
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