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» Complexity of Boolean Functions on PRAMs - Lower Bound Techn...
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ICCAD
2010
IEEE
140views Hardware» more  ICCAD 2010»
13 years 3 months ago
Reduction of interpolants for logic synthesis
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
John D. Backes, Marc D. Riedel
FPGA
1998
ACM
146views FPGA» more  FPGA 1998»
13 years 10 months ago
Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation
In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but a...
Jason Cong, Yean-Yow Hwang
UC
2005
Springer
13 years 11 months ago
On Computational Complexity of Counting Fixed Points in Symmetric Boolean Graph Automata
Abstract. We study computational complexity of counting the fixed point configurations (FPs) in certain classes of graph automata viewed as discrete dynamical systems. We prove t...
Predrag T. Tosic, Gul A. Agha
COCO
2009
Springer
106views Algorithms» more  COCO 2009»
14 years 11 days ago
Improved Approximation of Linear Threshold Functions
We prove two main results on how arbitrary linear threshold functions f(x) = sign(w · x − θ) over the n-dimensional Boolean hypercube can be approximated by simple threshold f...
Ilias Diakonikolas, Rocco A. Servedio
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
13 years 11 months ago
Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition
This paper addresses two problems related to disjointsupport decomposition of Boolean functions. First, we present a heuristic for finding a subset of variables, X, which results...
Andrés Martinelli, Elena Dubrova