18 search results - page 1 / 4 » Complexity reduction in an nRERL microprocessor |
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
ITC
1998
IEEE
13 years 8 months ago
1998
IEEE
This paper explores defects found in a high volume microprocessor when shipping at a low defect level. A brief description of the manufacturing flow along with definition of DPM i...
ISCA
1996
IEEE
13 years 8 months ago
1996
IEEE
This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory laten...
CF
2005
ACM
13 years 6 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
IPPS
2007
IEEE
13 years 10 months ago
2007
IEEE
This paper presents the performance improvements and the energy reductions by coupling a highperformance coarse-grained reconfigurable data-path with a microprocessor in a generic...