Sciweavers

2 search results - page 1 / 1
» Configurable and scalable high throughput turbo decoder arch...
Sort
View
ASAP
2008
IEEE
161views Hardware» more  ASAP 2008»
13 years 6 months ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval...
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
13 years 10 months ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...