5339 search results - page 1 / 1068 » Controllable Delay-Insensitive Processes |
FUIN
2007
13 years 4 months ago
2007
Abstract. Josephs and Udding’s DI-Algebra offers a convenient way of specifying and verifying designs that must rely upon delay-insensitive signalling between modules (asynchrono...
DELTA
2006
IEEE
13 years 8 months ago
2006
IEEE
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular struct...
ACSD
2004
IEEE
13 years 8 months ago
2004
IEEE
Abstract. A delay-insensitive module communicates with its environment through wires of unbounded delay. To avoid transmission interference, the absorption of a signal transition m...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— A mixed-signal architecture for continuous-time multidimensional model-free optimization is presented. It is based on multi-channel coherent modulation and detection that relia...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed...