275 search results - page 3 / 55 » Core architecture optimization for heterogeneous chip multip... |
ISCA
2006
IEEE
14 years 9 days ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
HPCC
2005
Springer
13 years 11 months ago
2005
Springer
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
PDP
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
ISCA
2005
IEEE
13 years 12 months ago
2005
IEEE
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...