27 search results - page 1 / 6 » Core-aware memory access scheduling schemes |
ICPP
2008
IEEE
13 years 11 months ago
2008
IEEE
On systems with multi-core processors, the memory access scheduling scheme plays an important role not only in utilizing the limited memory bandwidth but also in balancing the pro...
IPPS
2009
IEEE
13 years 11 months ago
2009
IEEE
Multi-core processors have changed the conventional hardware structure and require a rethinking of system scheduling and resource management to utilize them efficiently. However, ...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
FPL
2007
Springer
13 years 11 months ago
2007
Springer
In this paper, we propose a first step towards a time predictable computer architecture for single-chip multiprocessing (CMP). CMP is the actual trend in server and desktop syste...