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DATE
2000
IEEE
90views Hardware» more  DATE 2000»
13 years 9 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
DSN
2005
IEEE
13 years 6 months ago
Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors
The increasing transient fault rate will necessitate onchip fault tolerance techniques in future processors. The speed gap between the processor and the memory is also increasing,...
Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt
SAC
2009
ACM
13 years 11 months ago
An empirical study of incorporating cost into test suite reduction and prioritization
Software developers use testing to gain and maintain confidence in the correctness of a software system. Automated reduction and prioritization techniques attempt to decrease the...
Adam M. Smith, Gregory M. Kapfhammer
ICSM
2005
IEEE
13 years 10 months ago
An Empirical Comparison of Test Suite Reduction Techniques for User-Session-Based Testing of Web Applications
Automated cost-effective test strategies are needed to provide reliable, secure, and usable web applications. As a software maintainer updates an application, test cases must accu...
Sara Sprenkle, Sreedevi Sampath, Emily Gibson, Lor...
DFT
2000
IEEE
119views VLSI» more  DFT 2000»
13 years 9 months ago
An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications
1 Over the last years, an increasing number of safety-critical tasks have been demanded to computer systems. In particular, safety-critical computer-based applications are hitting ...
Maurizio Rebaudengo, Matteo Sonza Reorda, Marco To...