4 search results - page 1 / 1 » Cost Sensitive Modulo Scheduling in a Loop Accelerator Synth... |
MICRO
2005
IEEE
13 years 10 months ago
2005
IEEE
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
CODES
2006
IEEE
13 years 8 months ago
2006
IEEE
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
CASES
2009
ACM
13 years 11 months ago
2009
ACM
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...