33 search results - page 1 / 7 » Cost-Effective Approach for Reducing Soft Error Failure Rate... |
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
DFT
2003
IEEE
13 years 9 months ago
2003
IEEE
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
ISQED
2007
IEEE
13 years 10 months ago
2007
IEEE
Soft error due to ionizing radiation is emerging as a major concern for future technologies. The measurement unit for failures due to soft errors is called Failure-In-Time (FIT) t...