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» Cost-driven 3D integration with interconnect layers
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TCAD
2010
160views more  TCAD 2010»
12 years 11 months ago
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient netwo...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
ASPDAC
2011
ACM
207views Hardware» more  ASPDAC 2011»
12 years 8 months ago
Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip
Abstract— Three-dimensional (3D) integration and Networkon-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have b...
Cheng Liu, Lei Zhang 0008, Yinhe Han, Xiaowei Li
ASPDAC
2011
ACM
297views Hardware» more  ASPDAC 2011»
12 years 8 months ago
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequent...
Shashikanth Bobba, Ashutosh Chakraborty, Olivier T...
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 1 months ago
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems
Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical ...
Madhubanti Mukherjee, Ranga Vemuri
DAC
2010
ACM
13 years 8 months ago
Cost-driven 3D integration with interconnect layers
The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a p...
Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna ...